Description

Essential Duties and Responsibilities:

• The primarily responsible for design of advanced semiconductor packages, including both ceramic and organic substrates, including layout, parasitic extraction, and optimization
• Work with IC design, system design, package Signal Integrity (SI)/Power Integrity (PI) & thermal engineering teams to design custom interposer and substrates
• Work with SoC design teams to optimize die floorplan, bump patterns and interposer / substrate stack up
• Work with IC design team to define IC package requirements
• Design package layout using standard CAD tools
• Extract package parasitics and conduct PI/SI analysis
• Documentation and release in appropriate archival system

Requirements

Preferred Knowledge, Skills, And Abilities 

Layout:

Allegro Package Designer Plus (APD+) tools for designing the package and generating artwork for fabrication.
Analysis:

Celsius PowerDC (IR Drop)
Sigrity Advanced SI II: Analysis tools for Signal integrity of parallel busses (DDRx) and serial links (PCIe Gen x), including Package and PCB effects
Sigrity Advanced PI II: Power Integrity tools (IR drop, Impedance Profile, capacitor optimization) including Package and PCB effects
RF / Microwave Design

AWR, Momentum and HFSS Software Circuit, system, and EM simulation for RF/microwave product development

Qualifications

• Bachelors degree in Electrical Engineering, Mechanical Engineering, or other semiconductor packaging related discipline
• 8 to 10 years of experience in semiconductor packaging design, modeling, and simulations
• Strong authority on Cadence Allegro Package Designer Plus (APD+)
• Experience on interposer and substrate layouts and design in advanced package technologies
• Experience with 2.5D, 3D package design
• Experience with design teams on floor plan, bump and layout optimization
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated
• Record of success in cross-functional team environment
• Good experience with SI/PI tools for package level extraction/simulation